The present invention relates in general to BICMOS logic circuits (bipolar and CMOS circuitry on the same chip), and more particularly to a new family of logic circuits with improved power delay product while still maintaining the low power dissipation, high input impedance and the high noise immunity of the CMOS devices on the one hand, and the high drive capabilities of the bipolar devices on the other hand.
Several BICMOS circuits have been described in the literature. All of these circuits work on the same principle: bipolar transistors operate as a push-pull current booster, while Field Effect Transistors (NFET's and PFET's) are intended to constitute logic functions and to drive the base current of the bipolar transistors. In other words, in an optimized circuit designed to obtain the best use of both bipolar and unipolar technologies, FET's are used for logic implementation, and bipolar transistors for load driving.
Examples of such optimized circuits, are given in the following references:
Ref. 1: "How Motorola Moved BIMOS Up To The VLSI Levels," Electronics, Jul. 10, 1986, pp. 67-70.
Ref. 2: "CMOS/Bipolar Circuits for 60 MHz Digital Processing" by T. Hotta et al, IEEE Journal of SSC, Vol. SC-21 No. 5, October 1986, pp. 808-813.
Ref 3. "A Subnanosecond BI-CMOS Gate Array Family" by H. Nakashiba et al, IEEE 1986, Custom Integrated Circuits Conference, pp. 63-66.
FIGS. 1A and 1B of the present application depict two known BICMOS NAND gate circuits as published in references 1 and 2 respectively.
FIG. 1A shows a standard implementation of a two input BICMOS NAND gate circuit referenced 10, with FET and bipolar devices, as illustrated in FIG. 3 of Ref 1.
From FIG. 1A, it may be understood that the logic block Fp is built with PFET's P11 and P12. F.sub.P and Fn provide the base current to NPN transistors T11 and T12, respectively, when these transistors are turned on. T11 and T12 are the pull-up and pull-down transistors respectively of the gate circuit, and act as the driving devices for the next stages The common node between emitter of T11 and collector of T12 is the output node referenced OUT and is connected to the output terminal where the logic function F performed by the gate circuit is available.
To cut off T11, electric charges stored at the node UP must be evacuated. This discharge is controlled by the logic block F1 comprised of N13 and N14, similar to Fn. However, it is to be noted, that the discharge can also be done through a resistor (such as referenced Z in Ref. 3).
For the same reason, to cut off T12, node DN is discharged by a discharge device Z11 such as a feedback NFET, the gate of which is tied to the UP node (it might be connected to the OUT node as well). Node DN might also be discharged by a resistor (such as referenced Z in Ref 3).
The logical operation of the NAND gate circuit shown in FIG. 1A may be explained as follows
When input A or B (or both) is "low" (`0` logic), the node UP is set at the same voltage as Vdd by PFETs, T11 is turned on, while T12 is cut off because of the "off" state of the two NFETs, so that output OUT is set to "high" (`1` logic).
When inputs A and B are both "high", none of PFETs is conducting, T11 is off, while T12 is turned on by the NFETs Output OUT is set to "low".
Now, let input A (or B) go from "high" to "low", the other one staying "high", one of PFETs P11 (or P12) will turn on T11, while the T12 base is no longer biased into conduction because N11 (or N12) is set to the off state. Therefore, the output will go from "low" to "high". Accordingly the logic function f=A.multidot.B is available at output OUT.
FIG. 1B shows another embodiment of a two input BICMOS NAND gate circuit similar to the one shown in FIG. 2A of Ref. 2. The circuit of FIG. 1B referenced 11 has some similarities with circuit 10 of FIG. 1A. However, logic block F1 comprised of N17 and N18 is now connected to the ground instead of the DN node, and the discharge device Z12 is a resistor.
The capacitive load at the output node OUT is charged up or discharged with the NPN transistors T13 or T14 respectively. In short, the NPN transistors operate as a set of current boosters. In this circuit, the electric charges stored at the base nodes UP and DN flow out through the F1 block comprised of N 17 and N18 and the resistor Z12, respectively. This discharge contributes to speed-up and power-reduction by minimizing the time when the both NPN transistors are active. The logic operation is quite the same as explained above.
What should be noted is that the two input BICMOS NAND circuit of FIG. 1B may be understood as being comprised of both a pull up block 12 and a pull down block 13.
The pull down block 13 is comprised of N15, N16 and T14, whilst the pull up block 12 is comprised of N17, N18, P13, P14 and T13. These blocks are coupled at one point which is the output node OUT connected to the OUTPUT terminal where the logic function F is available.
In both cases shown in FIGS. 1A and 1B, a BICMOS NAND gate circuit has been chosen for the sake of simplicity. It exhibits high performance, low power consumption, and ease of configuration. According to the basic philosophy of the BICMOS technology, the circuit uses a pair of push-pull bipolar devices to provide the needed driving capability, while the low power requirements of CMOS are preserved because the circuit draws no D.C. current. These characteristics allow any CMOS circuit to be modified into a BICMOS structure. The bipolar push-pull devices isolate the CMOS circuits from the loading, so that unit load degradation is the same for all circuit functions. In addition, power dissipation is lower than in an equivalent bipolar circuit, and average power dissipation is even less than in an equivalent CMOS circuit.
One of the problems of this type of circuit is the relatively slow rising and falling signals at node UP, due to the use of heavily loaded FETs (one PFET and one NFET per logic input) connected to the pull up transistor in the emitter follower. When several inputs are used, the logic function that drives node UP is performed by several CMOS devices. For instance, the Fp and Fn blocks of a 4 way NAND will be composed of 4 PFET's in parallel and 4 NFET's in series. It is well known that such CMOS logic circuits have low rise and fall transitions: the greater the number of inputs, the slower the transitions. In addition to impacting the propagation delay, the increase of transition time when both NPN transistors are turned on, causes a crossover current which flows from Vdd to ground through said NPN transistors, thus power consumption increases. This phenomenon is a significant deficiency with submicron devices.
It is therefore a primary object of the present invention to provide a new family of BICMOS logic circuits, the speed performance of which does not degrade when the number of logic inputs increases.
It is still another object of the present invention to provide a new family of BICMOS logic circuits with quick charge or discharge at the UP node, to improve speed and reduce power consumption by minimizing the time when both NPN transistors are active.
It is still another object of the present invention to provide a new family of BICMOS logic circuits having reduced cross over currents when both NPN transistors are active.